VHDL Clock divider -

I am using the following VHDL to take a 100 MHz clock and put 25 MHz clock. :

  process (CLK, reset) variable number: integer range from 0 to 2; Then start (reset = '1') then clock_25MHz & lt; = '0'; Count: = 0; Elsf RID_Age (CLK) count then: = count + 1; If (calculation> = 2) then clock_25 MHz & lt; = Clock_25MHz; Count: = 0; end if; end if; end process;   
 This is warning me:  
 "WARNING: Xst: 1293 - FF / LoC Count_1 has a stable value of 0. It is FF / Latch Sorted during the optimization process. " 
 I do not understand why this is happening, can someone put some light on it for me? Thanks!   
 
 
 You do not need 2-bit calculation A single flop flop is sufficient.  
 If you add an integer signal CNT which has been counted (allowing me to see it on the wave with ghdl):  
  library ieee ; Use ieee.std_logic_1164.all; Unit clk_div is the end unit; Clk_div's architecture is foo signal clk: std_logic: = '0'; Signal reset: std_logic: = '1'; Signal clock 265 MHz: std_logic; Signal CNT: integer; Start CLKDi: Process (CLK, Reset) variable number: integer range from 0 to 2; Then start (reset = '1') then clock_25MHz & lt; = '0'; Count: 0 =; Elsf RID_Age (CLK) count then: = count + 1; If (calculation> = 2) then clock_25 MHz & lt; = no clock_25MHz; Count: 0 =; end if; end if; Cnt & lt; = Calculation; end process; Clock: Process starts waiting for 5 ns; CLK & LT; = No clock; If now & gt; 200 ns then wait; end if; end process; UNRESET: The process starts waiting for 20 ns; Reset & lt; = '0'; stop; end process; End architecture;   
 You find:  
   
  Counts  always appears as 1 or 1, 2 or 3, because you give it up to 0, whenever its 2 or more. It never shows on the edge of a clock  
 Is that correct? Why yes it is if you clock_25MHz standing 4 100 MHz watch at the waveform with clocks it works perfectly. Whatever you are processing is not necessary, the range of 0 to 2 is not required in the count, (two flip flops are required).  
 Change the evaluation order for the count, then the clock counts 265 MHz = 1, then toggle the count, change the counting range to 0 to 1 or better, even then type it std_logic.  
  - C संकेत: integer; Hint toggle_ff: std_logic; Start CLKDi: Process (CLK, Reset) - Good calculation: Integer range from 0 to 2; Variable toggle: std_logic; Then start (reset = '1') then clock_25MHz & lt; = '0'; - Count: = 0; Toggle: = '0'; Elsf raises_ege (CLK) then - count: = count + 1; - If (calculation> = 2) then if toggle = '1' then clock_25 MHz & lt; = clock_25MHz; - Count: = 0; end if; Toggle: do not toggle; end if; - Cnt & lt; = Calculation; toggle_ff & lt; = Toggle; end process;   
 gives:  
   
 You can also use a hint in the process statement, to toggle the toggle_name in my example code, remove the variable toggle declaration and the toggle_f signal assignment statement Remove The reason for this will work basically, because you evaluate the output of Google FF before the toggle.