Verilog Error: output or inout port "Q" must be connected to a structural net expression -

I get the error every time, I try to compile. I'm not sure why anyone can help is? I'm new to verilog.

  Module D_FF (clerk, d, reset_n, q); Input D, Clack, reset_en; Output Q; reg Q; lab4_gdl f1 (.lk (~ clk), d (d), .q.m (qm)); lab4_GDL f2 (.Clk (Clk), D (QM), .Q (Q)); Always start at @ (posedge clk, neggeous reset_n) (Reset_n == 0) Q & lt; = 0; Other questions & lt; = D; Edit End: The problem is what we are asking to do:  
 In this section, you apply the memory / registration circuit on the AlterEdie 2 board. will do. The circuit has the following specifications:  
 
 
 The present value of swift SW15-0 on the D2 board should be shown in four hexadecimal four sections of HEX3-0. This part of the circuit will be combination logic.   
 
 To use an active-less asynchronous reset and KEY1 to use KEY0 as the clock input, you must store SW15-0in in a 16-bit register in the value The register should be enabled to have a 16-bit positive edge, which uses the embedded D flip-flops in Elter FPGA. You can either trigger the D flip-flops or write a behavioral Verilog model for your register. The contents of this register should always be shown on Seven Seven Sections HEX7-4   
 Write a Verilog file which provides the necessary functionality KEY0 as an active-less asynchronous reset Use, and use KEY1 as clock input. You should be able to reuse your hex-to-seven segment display module from the final lab. When reset is pressed, hex 7-4 will display all the zeros.              , GPIID, hex , Hex1, hex2, hex3, hex 4, hex5, hex6, hex 7); Parameter n = 32; // Number of bits in the update counter input [0: 0] SW; // upgrade switch 1 = up, 0 = input down [0: 0] key; // key [1] = clock, key [0] = reset_en input [0: 0] GPIO_0; Output [0: 6] Hex 0, hex 1, hex 2, hex3, hex 4, hex5, hex 6, hex 7; Output [N -1: 0] LDR; // Display the binary count (active high) on red LED output [1: 0] LEDG; // display clock on LEDG [1], Reset_n at LEDG [0] wire clock, Reset_n, Updown; reg [n-1: 0] calculation; Specify clock = GPIO_0 [0]; Reset_n = Assign Key [0]; Exchange = SW [0]; LEDR = Calculate; Allocate to LGG [1: 0] = {clock, reset_en}; Always @ (posedge clk, negedge reset_en) // clock = clk if (Reset_n == 0) // Active-less asynchronous reset Q & lt; = 0; Other questions & lt; = D;    (Clerk, d, q); Input Clack, D; Output Q; Wire R_g, S_g, Qa, Qb / * synthesis * /; Assign R = ~ D; Assign R_g = ~ (R & amp; Clk); Assign S_g = ~ (D & amp; Clk); Assign Qb = ~ (R_g and QA); Q = Assign (S_g & Qb); Assign Q = Qa; Without looking at the code of  lab4_GDL , my guess is that the     
 
 
 It is that the  Q  module of the  lab4_GDL  module is an output port, you should not connect one output to the  reg  in the upper module.