flip flop - Verilog DFF Simulation Producing x for Output -


It should be the easiest issue to sort, but for some reason I can not understand it I currently own Verilog Reading and developing these are very basic modules and test benches for these modules as a practice. One of these modules is D flip flop (DFF). Here is the DFF module (no reset): 

  module DFF (CLK, D, Q); Parameter n = 1; // DFF width input clock; Input [N -1: 0] D; Output [N-1: 0] Q; Reg [n-1: 0] q; Always @ (posedge clk) Q & lt; = D; And end module   
 And here is the test bench:  
  module dff_tb; Reg Clack, D; reg Q; DFF # (1) DUT (CLK, D, Q); Initial start clk = 1'b0; Forever # 10 clk = ~ clk; // Generate clock end of initial D = 0; // Check D = 0 if (Q! == 0) $ display ("[unsuccessful] Q = 0"); # 40d = 1; // Check D = 1 # 40 if (Q! == 1) $ display ("[unsuccessful] Q = 1"); $ Over; // complete trial end endmodule   
 and the simulation is here: Enter image details Here   
 Test Bench Reg Q is X for the simulation period (thought [0] does not question ...).  
 Why any thoughts? Thanks!   
 
 
 You do not reset your flop, so before the clock edge, there is no Q Known value  
 Usually a flop has an async reset, which should be specified at the beginning of the simulation in your test bench. Always be in your FF block:  
  always @ (reset posedge clk or posedge) if (reset) Q & lt; = '0; Other questions & lt; = D; End   
 In addition, you do not need to define the Q as reg. It can be wired    Working code

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