Continuous assignment verilog -


- This code has been written in Verizon using MediSidem 10.2 D. The errors below indicate that {cout, l3} assignments. Module ALU (A, B, Bin, Pin, Op, Cot, Race); Input [31: 0] A, B; Input [1: 0] op; Input bin, cin; reg [31: 0] L1, L2, L3; Output Cout; Output [31: 0]; L1 = Assign and assign; B; l2 = a | Assign b; Assign the initial if (bin == 1'b 0) {cout, l3} = a + b + cin; Again assign {cout, l3} = a - b + cin; mux4to1 (L1, L2, L3, op, race); Endmodule error-v (14): In the procedural continuous assignment the LHS may not be pure: cout. v (16): LHS in the procedural continuous assignment can not be a pure: cout

the wire can not be assigned inside initial or always you should change the type to reg .

The initial block will be played only once at the beginning of the simulation, not constantly evaluated, so you should always always instead 

  //. .. output reg cout; // ... always start @ * if (bin == 1'b 0) {cout, l3} = a + b + cin; End and start {cout, l3} = a - b + cin; End End

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