verilog - endmodule error while compiling -


I'm trying to code a memory test algorithm in Verilog. This code is a part of it. I am trying to write a state machine to read the signal to read.

Any help would be appreciated.

p> This is my code: 

  module exam (q, clk, reset, data_in, r_s); Input clique; Input reset; Output [0: 2] Q; Output data_in; Output r_s; Reg data_in; reg [0: 2] Q; // address space reg [0: 2] state; // state machine reg r_s; Integer = 0; Reg [0: 1] l = 0; Always start @ (posedge clk or posedge reset or state) start 1 / if (reset) state & lt; = 1; Q & lt; = 0; End and start case (state) 1: // Begin the first four steps (8) Start @ (posedge clk) (start!) Start case (L) 0: Start q & lt; = q; End 1: Start q & lt; = q; End 2: Start q & lt; = q; End 3: Start q & lt; = Q + 1; Did & lt; = 1; And Endes and End @ (Neighage CLK), while (! Work) start case (L) 0: Start L  
 You do not have an" end "between the end of the label with" end-repeating "and" endcase "comments ( Because it is "starting" before starting again, which must be closed before closing this matter).  
 This is not entirely clear because the Indentation style you are using I'm confused. Was able to index, so I could see what was happening, and I suggest using a style closer to this style in the future because it makes it easier to find such problems:  
  module test q, clk, reset, data_in, r_s); input clack; input reset; output [0: 2] q; output data_in; output r_s; ​​reg data_in; reg [0: 2] cue ; // Address Space reg [0: 2] State; // state machine reg r_s; ​​integer = 0; reg [0: 1] l = 0; always @ (posedge clk or posedge reset or state) start 1 / if (reset) state starts & lt; = 1; q & lt; = 0; end and start case (state) 1: // first four phases repeat start (8 ) Start @ (posedge clk) while starting (! Done) Start case (L) 0: Start q & lt; = q; End 1: Start q & lt; = q; End 2: Start q & lt; = Q; End 3: Start q & lt; = q + 1; Did & lt; = 1; And Endes and End @ (Neighegs CLK), while (! Work) case to start (L) 0: Start L

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