Verilog error for 2d array declaration -


  • I wrote this code for the register file in verilog.

  • I'm using ModelSim Altera 10.1d 

       < Li> 
     Model Regefile (CLK, Reset, Redridge 1, RedRag 2, LikedData, Written, Regrite, Reddata 1, Redidata 2); Input clique, reset, resize; Input [1: 0] ReadReg1, ReadReg2, WriteReg; Input [31: 0] Write data; Output [31: 0] ReadData 1, ReadData 2; Reg [31: 0] D, Q1, Q2, Q3, Q4, Q; Reg [3: 0] Datap; Reg clkwrite, reg [31: 0] data [3: 0]; Reg [31: 0] read1, read data 2; Initial start d = 32'h00000000; Data [0] = 32'd101; Data [1] = 32'd234; Data [2] = 32'd260; Data [3] = 32'd120; End always start (reset) reg32bit (q1, d, clk, reset) if start (@posedge clk); reg32bit (Q2, D, clk, reset); reg32bit (Q3, D, clk, reset); reg32bit (q4, d, clk, reset); End and Start / Write Decoder 2_4 (decoutp, WriteReg); clockgate (clkwrite, RegWrite, clk, decoutp); reg32bit (q, writeData, clkwrite, reset); // Read (ReadReg1 == 2'b00) ReadData1 = Data [0]; Else if (ReadReg1 == 2'b01) ReadData1 = Data [1]; Else if (ReadReg1 == 2'b10) ReadData1 = Data [2]; else ReadData1 = data [3]; If (ReadReg2 == 2'b00) ReadData2 = Data [0]; Else if (ReadReg2 == 2'b01) ReadData2 = Data [1]; Else if (ReadReg2 == 2'b10) ReadData2 = Data [2]; And ReadData2 = data [3]; Error: -  
     (1) v (9): pass "reg": syntax error, unexpected reg, expect IDENTIFIER or 
     TYPE_IDENTIFIER  
     (2) v (15 ): (vlog-2730) Undefined variable: 'data'.     
     
     
     It seems that you have a typo after the ClerkLight declaration There is a comma.

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